4:1 MULTIPLEXER IN XILINX ISE 9.1i

-- Company:
-- Engineer:
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-- Create Date:    15:19:42 03/09/2013
-- Design Name:
-- Module Name:    ANIMULTIPLEXER - Behavioral
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-- Company:
-- Engineer:
--
-- Create Date:    22:02:51 05/12/2013
-- Design Name:
-- Module Name:    ANIMULTIPLEXER4TO1 - Behavioral
-- Project Name:
-- Target Devices:
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-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ANIMULTIPLEXER4TO1 is
    Port ( IO : in  STD_LOGIC;
           I1 : in  STD_LOGIC;
           I2 : in  STD_LOGIC;
           I3 : in  STD_LOGIC;
           SEL : in  STD_LOGIC_VECTOR (1 downto 0);
           O : out  STD_LOGIC);
end ANIMULTIPLEXER4TO1;

architecture Behavioral of ANIMULTIPLEXER4TO1 is

begin

PROCESS(IO,I1,I2,I3,SEL)
BEGIN
CASE SEL IS
WHEN "00" => O<=IO;
WHEN "01" => O<=I1;
WHEN "10" => O<=I2;
WHEN OTHERS => O<=I3;
END CASE;
END PROCESS;

end Behavioral;