FULL ADDER IN XILINX ISE 9.1i

-- Company:
-- Engineer:
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-- Create Date:    15:39:58 03/02/2013
-- Design Name:
-- Module Name:    ANIFA - Behavioral
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-- Target Devices:
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-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANIFA is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : in  STD_LOGIC;
           S : out  STD_LOGIC;
           Co : out  STD_LOGIC);
end ANIFA;
architecture Behavioral of ANIFA is
begin
S <= (A XOR B) XOR C;
Co <= (A AND B) OR (C AND (A XOR B));
end Behavioral;