4:1 MULTIPLEXER IN XILINX ISE 9.1i

-- Company:
-- Engineer:
--
-- Create Date:    15:19:42 03/09/2013
-- Design Name:
-- Module Name:    ANIMULTIPLEXER - Behavioral
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-- Company:
-- Engineer:
--
-- Create Date:    22:02:51 05/12/2013
-- Design Name:
-- Module Name:    ANIMULTIPLEXER4TO1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ANIMULTIPLEXER4TO1 is
    Port ( IO : in  STD_LOGIC;
           I1 : in  STD_LOGIC;
           I2 : in  STD_LOGIC;
           I3 : in  STD_LOGIC;
           SEL : in  STD_LOGIC_VECTOR (1 downto 0);
           O : out  STD_LOGIC);
end ANIMULTIPLEXER4TO1;

architecture Behavioral of ANIMULTIPLEXER4TO1 is

begin

PROCESS(IO,I1,I2,I3,SEL)
BEGIN
CASE SEL IS
WHEN "00" => O<=IO;
WHEN "01" => O<=I1;
WHEN "10" => O<=I2;
WHEN OTHERS => O<=I3;
END CASE;
END PROCESS;

end Behavioral;

OR GATE IN XILINX ISE 9.1i

-- Company:
-- Engineer:
--
-- Create Date:    15:34:56 02/23/2013
-- Design Name:
-- Module Name:    ANI_OR_GATE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANI_OR_GATE is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end ANI_OR_GATE;
architecture Behavioral of ANI_OR_GATE is
begin
c<=a OR b;
end Behavioral;

NAND GATE IN XILINX ISE 9.1i

-- Company:
-- Engineer:
--
-- Create Date:    15:50:17 02/23/2013
-- Design Name:
-- Module Name:    ANI_NAND - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANI_NAND is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : out  STD_LOGIC);
end ANI_NAND;
architecture Behavioral of ANI_NAND is
begin
C <= A NAND B;
end Behavioral;

HALF SUBTRACTOR IN XILINX ISE 9.1i

-- Company:
-- Engineer:
--
-- Create Date:    14:36:46 04/06/2013
-- Design Name:
-- Module Name:    ANIHS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANIHS is
    Port ( A : in  STD_LOGIC;
           Bin : in  STD_LOGIC;
           Bout : out  STD_LOGIC;
           D : out  STD_LOGIC);
end ANIHS;
architecture Behavioral of ANIHS is
begin
D <= A XOR Bin;
Bout <= (NOT A) AND Bin;
end Behavioral;

HALF ADDER IN XILINX ISE 9.1i

-- Company:
-- Engineer:
--
-- Create Date:    16:30:51 02/23/2013
-- Design Name:
-- Module Name:    ANI_HA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANI_HA is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : out  STD_LOGIC;
           S : out  STD_LOGIC);
end ANI_HA;
architecture Behavioral of ANI_HA is
begin
S <= A OR B;
C <= A AND B;
end Behavioral;

FULL SUBTRACTOR IN XILINX ISE 9.1i

-- Company:
-- Engineer:
--
-- Create Date:    14:52:14 04/06/2013
-- Design Name:
-- Module Name:    ANIFS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANIFS is
    Port ( A : in  STD_LOGIC;
           Bin : in  STD_LOGIC;
           C : in  STD_LOGIC;
           D : out  STD_LOGIC;
           Bout : out  STD_LOGIC);
end ANIFS;
architecture Behavioral of ANIFS is
begin
D <= A XOR (Bin XOR C);
Bout <= (((NOT A) AND (Bin XOR C)) OR (Bin AND C));
end Behavioral;

FULL ADDER IN XILINX ISE 9.1i

-- Company:
-- Engineer:
--
-- Create Date:    15:39:58 03/02/2013
-- Design Name:
-- Module Name:    ANIFA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANIFA is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : in  STD_LOGIC;
           S : out  STD_LOGIC;
           Co : out  STD_LOGIC);
end ANIFA;
architecture Behavioral of ANIFA is
begin
S <= (A XOR B) XOR C;
Co <= (A AND B) OR (C AND (A XOR B));
end Behavioral;