HALF SUBTRACTOR IN XILINX ISE 9.1i

-- Company:
-- Engineer:
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-- Create Date:    14:36:46 04/06/2013
-- Design Name:
-- Module Name:    ANIHS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANIHS is
    Port ( A : in  STD_LOGIC;
           Bin : in  STD_LOGIC;
           Bout : out  STD_LOGIC;
           D : out  STD_LOGIC);
end ANIHS;
architecture Behavioral of ANIHS is
begin
D <= A XOR Bin;
Bout <= (NOT A) AND Bin;
end Behavioral;