NAND GATE IN XILINX ISE 9.1i

-- Company:
-- Engineer:
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-- Create Date:    15:50:17 02/23/2013
-- Design Name:
-- Module Name:    ANI_NAND - Behavioral
-- Project Name:
-- Target Devices:
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-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANI_NAND is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : out  STD_LOGIC);
end ANI_NAND;
architecture Behavioral of ANI_NAND is
begin
C <= A NAND B;
end Behavioral;