OR GATE IN XILINX ISE 9.1i

-- Company:
-- Engineer:
--
-- Create Date:    15:34:56 02/23/2013
-- Design Name:
-- Module Name:    ANI_OR_GATE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ANI_OR_GATE is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end ANI_OR_GATE;
architecture Behavioral of ANI_OR_GATE is
begin
c<=a OR b;
end Behavioral;